Estoy diseñando un contador binario síncrono de 4 bits en vhdl y no se como hacerlo, he probado unas cuantas cosas pero no he dado con la buena. A ver si alguien me puede echar una mano. Lo quiero conseguir hacer con el generate y con la estructura de basculas T con and y replicarlas en serie.
Ésta es la imagen del SBC:
El código del componente es:
library ieee;
use ieee.std_logic_1164.all;
entity ETFF is
-- 1-bit enable rising-edge register
port(
T: in std_logic;-- Toggle enable
A_RES: in std_logic; -- Asynchronous reset
CK: in std_logic; -- Clock input
out_and: out std_logic; -- out and
Q: out std_logic -- Output
);
end ETFF;
architecture behavior of ETFF is
signal Qaux: std_logic;
begin
ff:process(CK, A_RES)
begin
if (CK'event and CK = '1') then
if (a_res = '1') then
Qaux<='0' after 10 ps;-- asynchronous reset condition
elsif (T='1') then
Qaux <= not(Qaux) after 10 ps;
end if;
end if;
end process;
out_and <= (Qaux and T);
Q <= Qaux;
end behavior;
Y el código contador de 4 bit que quiero hacer es:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sbc_total is
port (
CK : in std_logic;
ENABLE : in std_logic;
A_RES : in std_logic;
Q_OUT : out std_logic_vector(3 downto 0);
E_OUT : out std_logic
);
end sbc_total;
architecture arch of sbc_total is
--signal a_res_aux : std_logic_vector (3 downto 0);
signal q_aux : std_logic_vector (3 downto 0);
signal t_aux : std_logic_vector (3 downto 0);
signal out_and_aux : std_logic_vector (3 downto 0);
component etff
port(
T: in std_logic;-- Toggle enable
A_RES: in std_logic; -- Asynchronous reset
CK: in std_logic; -- Clock input
out_and: out std_logic; -- out and
Q: out std_logic); -- Output
end component;
begin
GEN_FF:for i in 1 to 3 generate
ETFF_i: ETFF
port map(
CK => CK, A_RES => A_RES, out_and => out_and_aux(i), T => t_aux(i), Q => q_aux (i), t_aux(i)=> out_and_aux (i-1));
end generate;
t_aux(0) <= ENABLE;
Q_OUT <= q_aux;
end arch;
