10/10/2006, 17:00
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 | Colaborador | | Fecha de Ingreso: abril-2003
Mensajes: 12.106
Antigüedad: 21 años, 9 meses Puntos: 25 | |
Pon atención especialmente al segundo parrafo: Cita: It is a common misconception that, if two devices of different speed capabilities are on the same cable, both will necessarily transfer data at the speed of the slower device. This is true only with very old chipsets or add-in adapters. All modern ATA interfaces (since, at least, the late Pentium III and AMD K7 era) support independent timing, which allows each device on the cable to transfer data at its own best speed.
However, due to the omission of both overlapped and queued feature sets from most real-world parallel ATA products, the preceding paragraph must be clarified. It applies to the data transfer phase, but this is usually the shortest part of a complete read or write operation. Devices do differ markedly in the total time required to perform an I/O (irrespective of the burst data transfer rate), and since only one device on a cable can have an operation in progress at one time, they do affect each others' performance. El artículo completo aqui: http://en.wikipedia.org/wiki/Advance...ogy_Attachment
__________________ "El hombre, en su orgullo, creó a Dios a su imagen y semejanza."Friedrich Nietzsche |